Computational Science & Maths Research

Genuine revolution in Computing, moving past von Neumann and Harvard models into combinatorially-accessible realms of universal computers, which are much more efficient and securable than our current, long-since-stagnated popular computational mathematics and technologies. Separately, another project that is also an evolution in Formal Logics.

Current publicly-visible projects:

• Ternary Instruction Set Computer
  
  • TISC is a ground-up rethink of computing especially useful for the HPC AI era: a balanced-ternary encoding, 26-directional 3-D-memory, 4-D-cursor general-purpose architecture that can deliver orders-of-magnitude gains in energy-per-compute while hardening security and slashing tool-chain complexity. The in-development Abstract Machine models full handling of arbitrary trits, trytes, and machine‐sized shapes; separate control, (multi)function, and (multi)data spaces & handling; and verifiable security, isolation, and hard‐real‐time guarantees, properties, and proofs.  By uniting open hardware licences with a Defensive Patent License “safe harbor”, TISC turns every grant dollar into freely-shareable IP that the whole research community can build on.  I do not want to engage in the State-biased "Patent Game", but I do want to prevent others from trying to patent any of this.
• Syādvāda Logic
  • This is a paraconsistent 7-value Formal Logic for use in innumerable contexts requiring combinatorial logical reasoning.
  • Syādvāda is a system of argumentation developed by Jaina philosophers to account for the complexity and multifaceted nature of reality. It is based on the idea that any given statement or claim about an object or phenomenon can be viewed from multiple perspectives, each of which may be true or false or neither depending on the context and the assumptions being made.
• Triologics
  • Families of paraconsistent Formal Logics of non-binary (i.e., >2) prime-number cardinalities also encompassing Syādvāda Logic.
  • These have use in even more contexts than mere Syādvāda Logic.

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I'm currently focusing my funding efforts on the Ternary Instruction Set Computer project.

Why Ternary, Why Now?

“ ...and perhaps the symmetric properties and simple arithmetic of this number system will prove to be quite important someday — when the ‘flip-flop’ is replaced by a ‘flip-flap-flop.’"

– Donald Knuth; Art of Computer Programming, Volume 2: Seminumerical Algorithms, 3rd Edition, Section 4.1

• Energy headroom is gone – modern CMOS scaling flat-lined; balanced-ternary arithmetic can cut switching events by up to 35% in arithmetic units and DRAM accesses, a saving recently confirmed in optical-ternary optimisation experiments. cf. nature.com

• AI workloads favor 3-value weights – ternary neural networks (TNNs) already outperform binary networks at the same power budget; the xTern ISA extension shows 57% better energy-efficiency on RISC-V cores with only 0.9% silicon overhead. cf. arxiv.org

• Neuromorphic inspiration – SpiNNaker 2’s multi-valued routing proved that extra voltage levels unlock massive fan-out for brain-scale models. cf. tomshardware.com

• Fabrication is ready – 3-D DRAM road-maps point to vertical cell arrays that are naturally addressed by TISC’s 3-D memory model and can better take advantage of TISC's 27-dimensional memory bandwidth. cf. newsroom.lamresearch.com

• Security can be built-in – capability machines such as Cheri or Zeno eliminate whole classes of memory exploits at hardware level. TISC also makes use of capabilities. cf. arxiv.org

• HPC workloads will be vastly accelerated – given in the design of TISC the care put into allowing and opening as many avenues for HW and SW optimization as possible, especially combinatorial.

 

Classical CPU	TISC innovations
Flat, address-based RAM	Hierarchical, 26-connected 3-D Memory, allowing for typical 27-dimensional memory access; triplicated into Data, Behavior, & Control spaces for cache-friendly locality and instant control-code-data separation.
Program counter & registers	4-D Cursors (3D + Time) move through space instead of shuffling data, cutting traffic and enabling dataflow scheduling.
Von-Neumann pipeline	Separate Control from Behavior and Data constrains the mode of Computation even more than a Harvard architecture does, leaving ample room for static and dynamic guarantees and radical optimizations. Conveyor-belt PDA (inspired by Mill architecture), as any traditional "Stack Machine", removes costly rename logic and promises ≥10× single-thread performance per Watt. Stacks (V(isibly)PDAs, not PDAs), whose preferential use allow for many temporal guarantees and otherwise-impossible optimizations.
Paged MMU	Region-&shape-aware memory with compile-time safety; draws on decades of region-based analysis to end use-after-free bugs, and trivial alias analysis.
Ad-hoc privilege rings	Fine-grained capability tickets enforced in HW for zero-copy, zero-trust sharing. 5 medium-grained Rings tailored to particular levels of the Computation model. 3 coarse-grained separate Memory Spaces; for Data, Behaviors, and Control.

AI/ANN use cases can Fuel

While not specifically designed with ANNs in mind, the architecture lends itself very well to this currentlly-hot area given its HPC goals. Besides better FMA and ternary multipliers as noted above:

• Sparse-aware dataflow – TISC’s cursor moves instead of gathers, ideal for the pointer-heavy graphs of GNNs and transformer attention.

• Rational encodings – The available ranges of fixed-point fractions cover weight usages in all ANN architectures: (0,1), (1,2), (-2,-1) ∪ (1,2), and (-1,1).
  • Rational Neural Networks with rational activation
    functions σ(x) = P(x)/Q(x) require exponentially smaller depth than ReLU networks.

• Edge-ready – The 2025 Edge-AI Technology Report highlights ultra-low-power TNN inference as a top industry priority, a sweet-spot for TISC evaluation boards. cf. ceva-ip.com

Open Maths, Science, and "IP"

All “IP” licensing is layered with the Defensive Patent License. Idris2 (and possibly Coq), Racket/Redex, C/++, and Gem5 code and proofs will be FOSS, under an AGPLv3+-esque license.  Hardware RTL/layout will also be FOSS, under a CERN OHL-v2-S-esque license. Until the Imperial Powers end and/or a better-accepted global structure than the UN emerges, both are additionally subject to the Hippocratic License 2.1.
This means: zero licence fees, maximum academic visibility, and no room for rent-seeking intermediaries.

Me, myself

I'm Alex Márquez Pérez, a mathematician by vocation, computer scientist and formal semanticist by training, and software engineer by trade. I've over a decade of experience blending deep practical expertise with scholarly rigor in programming languages and computer architecture. My industrial career includes impactful roles at Google and Microsoft where I've implemented theory into robust, production-ready systems—such as migrating Android's build infrastructure to Bazel or developing a soft-real-time embedded OS for military-grade communications.

Before my industry work, my academic path has been even more rigorous and impact‑driven. As a doctoral researcher at Northeastern University, I investigated static analysis, verified compilers, and temporal logics for a DARPA‑funded Android‑security project, while also teaching Fundamentals under Dr. Matthias Felleisen. Before that, I completed both my master’s and two bachelors' degrees in Computer Science at Georgia Tech—graduating from the inaugural Honors Program—where my theses spanned programming‑language design and machine‑learning‑driven AI. During my graduate tenure, I joined the DARPA UHPC (Ubiquitous High Performance Computing) initiative, creating Cetus‑UHPC, a source‑to‑source analysis framework that yields algebraic metrics for next‑generation HPC architectures. Earlier still, as an undergraduate researcher I co‑developed AFABL, a reinforcement‑learning‑backed language for agent‑based simulations, laying the groundwork for my continuing interest in formally verified, adaptive systems. I'm proficient across multiple languages — such as C, C++, Scala, Python, Idris2, and Racket — and I actively engage in open-source contributions.

My academic foundations reinforced my specialization in static analysis, compiler verification, and high-performance computing—knowledge I'm directly channeling into my current project, the Ternary Instruction-Set Computer (TISC). This project is being meticulously documented and is being coded with proofs for formal verifications.

My commitment to rigorous documentation, practical implementations, and transparency ensures that every investment in TISC directly translates into verifiable milestones, robust tooling, and openly shared results. Supporting my research means backing a comrade with a proven record of translating advanced theoretical insights into tangible technological advancements. Join me in replacing yesterday’s “flip-flop” with tomorrow’s flip-flap-flop. Let’s build the Computational Science that Donald Knuth merely foreshadowed!